ARM pronounces new Artemis CPU center, first 10nm test chip, constructed at TSMC

ARM and TSMC have had a joint agreement in vicinity for several years to collaborate on R&D work and early validation on process nodes, and that they’ve introduced a major milestone in that method. As of the day before today, ARM is saying that it has efficiently established a brand new 10nm FinFET design at TSMC.


The unnamed multi-core test chip features a quad-middle CPU from ARM, codenamed Artemis, a single-middle GPU as a proof of concept, and the chip’s interconnect and other various functions.


This isn’t an SoC that ARM will ever convey to marketplace. alternatively, it’s reason is to feature as a validation tool and early reference layout that allows both TSMC and ARM recognize the specifics of the 10nm FinFET system as it movements in the direction of industrial viability. one of the functions that natural-play foundries like TSMC offer their customers are equipment and libraries particularly designed to in shape the talents of each process node. on account that each new node has its personal design regulations and best practices, TSMC has to music its offerings as a result — and running with ARM to create a reasonably complex test chip is a win/win situation for each companies. ARM receives early insight into how first-rate to song upcoming Cortex processors; TSMC gets a preferred structure and SoC design that carefully corresponds to the actual chips it’ll be constructing for its customers as the new method node moves into production.


The slide above suggests the profits TSMC expects to realise from moving to 10nm in place of its contemporary 16nm process. To the nice of our information, TSMC’s 10nm is a hybrid technique, however it’s now not clear precisely what that hybrid seems like. Our modern know-how is that the imminent 10nm node might combine a 10nm FEOL (the front cease-of-line) with a 14nm BEOL (returned-stop-of-line, which governs die length). EETimes, but, reported in March that TSMC’s 10nm shrink could keep a 20nm minimum feature size, even as its 7nm might supply a 14nm minimal feature length (10/20 and seven/14, respectively). both manner, Intel is the best company that has announced a “authentic” 14nm or 10nm die cut back. (The diploma to which this method benefit materially allows Intel in recent times is open to discuss).


things to note: First, the top line of the slide is doubtlessly complicated. The zero.7x reduction of strength would be less difficult to read if ARM had labeled it “ISO performance at 0.7x power.” second, the performance gains expected right here in simple terms as a result of the node transition are downright anemic. I don’t want to read too much into those graphs because it’s very early days for 10nm, but there’s been plenty of speak around 16/14nm as a protracted-lived node, and results like this are a part of why — only a handful of corporations will want to pay the extra charges for the additional mask required as a part of the die cut back. TSMC has already stated that it believes 10nm might be a pretty quick-lived node, and that it thinks it’ll have extra extensive client engagement for 7nm.

None of because of this ARM can’t supply compelling enhancements at 10nm — however the constrained quantity of lithography upgrades imply a heavier lift for the CPU research groups and layout group of workers, who want to find additional hints they are able to use to squeeze extra overall performance out of silicon without riding up strength consumption.

As for whilst 10nm might ship, past timelines endorse it’ll be some time but. TSMC has stated it expects early 10nm tapeouts to pressure vast call for starting in Q2 2017. at the same time as that’s a quick flip-round for a organization whose 16nm most effective entered volume production in August 2015, the speed can be explained if the 10nm node keeps to leverage TSMC’s existing 20nm era. undergo in mind that there’s a big postpone among whilst TSMC generally ships hardware and whilst consumer products release, particularly in mobile gadgets wherein multiple groups carry out complicated verification strategies on multiple parts of the chip.

either way, this tapeout is a great breakthrough for both ARM and TSMC, and 10nm will deliver improvements over the 16nm tech available today.